Integrated circuits (“ICs”) are formed in the “active” surface of a single die, or “chip,” cut from a semiconductor wafer containing an integral array of identical dies. The dies are relatively small and fragile, are susceptible to harmful environmental elements, particularly moisture, and during operation, can generate a relatively large amount of heat in a relatively small volume. Accordingly, ICs are typically assembled in affordable, yet robust, packages that protect them from the environment, enable them to be reliably mounted to and interconnected with, for example, a printed circuit board (“PCB”) populated with associated electronic components, and to effectively dissipate to the ambient the heat they generate during operation.
A recent trend in the electronics industry has been toward equipments that are smaller, lighter, and yet more functional. This has resulted in a concomitant demand for semiconductor packages that have smaller outlines and mounting “footprints,” yet increased functionality. One response to this trend has been the development of “chip-scale,” or “chip-size,” semiconductor packages, including ball grid array (“BGA”), land grid array (“LGA”), and lead-less chip carrier (“LCC”) packages, which are surface mounting devices that have outline and mounting dimensions only slightly greater than those of the semiconductor die packaged therein.
An example of one known type of such a chip size package, viz., a so-called “ball grid array” (“BGA”) semiconductor package 100, is illustrated in the top plan, cross-sectional elevation, and bottom plan views of FIGS. 5–7, respectively. As shown in the figures, the conventional BGA package 100 comprises a semiconductor die 102 soldered to and in electrical connection with an interconnective substrate 104, the latter serving both to redistribute the electrical input/output (“I/O”) signals to and from the die, and to assist in the hermetic sealing of the die against harmful environmental agents, including moisture.
A laminate type of substrate 104, such as the simple, three-layer embodiment illustrated in the figures, typically comprises one or more dielectric layers 106 on which one or more patterned metal layers 108 are formed. The metal layers 108 are patterned, typically by photo-etching techniques, to include signal connection pads 110 on the upper surface of the dielectric layer 106 and terminal lands 112 on the lower surface thereof. The connection pads 110 are connected to the lands 112 through the thickness of the substrate 102 by plated-through holes 114, called “vias.” The metal layers 108 may also be patterned to include circuit traces 116 on one or both surfaces of the dielectric layer 106 that connect one or both of the connection pads 110 and the lands 112 to each other through the vias 114.
In a conventional BGA package 100, balls 118 of a conductive metal, e.g., a lead-tin solder, are formed on respective ones of the lands 112, which are arranged in the form of a “grid,” or rectangular array, to serve as signal input/output and mounting terminals of the package 100. In LGA and LCC packages, the terminal balls 118 are omitted, and the lands 112 themselves serve as the package terminals.
To effect the signal redistribution function, signal I/O pads 120 on the active surface of the die 102 may be bonded to the signal connection pads 110 on the substrate 104 with fine, conductive wires (not illustrated), or alternatively, as illustrated in FIG. 6, soldered directly to the connection pads 110 using the so-called “flip-chip,” or “C4,” method of die attachment, typically with a flux and a solder comprising lead (Pb) and tin (Sn).
The “flip-chip” method of attaching chips to and in electrical connection with substrates was developed by, inter alia, IBM, Inc., in about 1965. Sometimes referred to as the “Controlled Collapse Chip Connection,” or “C4,” method (see, e.g., L. F. Miller, “Controlled Collapse Reflow Chip Joining,” IBM J. Res. Develop., 239–250, May 1969), the technique involves forming bumps of a conductive metal, e.g., solder, on the signal I/O pads 120 on the active surface of the chip 102, then inverting, or “flipping” the chip upside-down and “reflowing,” or fusing, the solder bumps to the corresponding connection pads 110 on the substrate 104, which is conventionally effected in a conveyor oven using a flux.
The package 100 is typically hermetically sealed by molding a dense body 122 of plastic, e.g., a filled epoxy resin, over the mounted die 102 and at least a portion of the substrate 104, or alternatively, by attaching, e.g., by soldering, a metal lid 124 (shown by dashed outline in FIGS. 5 and 6) to the substrate that covers the die. Prior to sealing, it is conventional to clean the narrow space between the die 102 and the substrate 104 thoroughly of any residual flux, then “underfill” the space with a layer 126 of a low-viscosity liquid plastic, which is then cured solid. The underfill layer 126 serves to support the die 102 above the substrate 104 and prevent the plastic of an encapsulating body 122 from penetrating into the space and forming a potentially destructive “thermal wedge” between the die and the substrate at elevated temperatures, or alternatively, to prevent any flux residue remaining in the package from the solder attachment of a lid from corroding the connection pads and the active surface of the die during the life of the package.
While the conventional BGA package 100 assembly techniques illustrated and described above afford a generally satisfactory solution to the need for a chip size semiconductor package, they are not without certain drawbacks. One of these relates to the need for using a flux in the soldering, or electrical attachment, of the die to the substrate, and the concomitant need to clean the assembly thoroughly of any flux residue before the package is sealed to prevent subsequent corrosion by the flux residue. The need for a flux in the die attachment process arises from the presence of oxide films that form on the solder and the connection pads as a result of the reaction of the metals in the solder and pads with oxygen in the atmosphere. The oxide films prevent the wetting by the solder of the surfaces to be joined. Fluxes strip and chemically bind with the oxide films at elevated temperatures and thereby “clean” the metal of the pads of any oxides and enable the solder to wet and join with the metal.
While it is possible to eliminate the use of a flux by first carefully cleaning the metal of the contacts of any oxide films and then effecting the soldering of the die to the substrate in a “reducing” atmosphere, e.g., one containing hydrogen, this procedure is relatively costly and involves the use of equipment that is complex, expensive, and potentially dangerous. It is therefore desirable to provide a method for soldering a first substrate, e.g., a semiconductor die to and in electrical connection with a second substrate, e.g., an interconnective substrate of a semiconductor package, without using fluxes or reducing atmospheres, or the complex cleaning processes that they entail.
Another drawback of the conventional package is the need for separate, costly processes and structures for hermetically sealing the active surface of the die and the electrical contacts between the die and the substrate from the ambient. It is therefore desirable to provide a method for hermetically sealing a semiconductor package without the need for these additional processes and materials, and further, to effect such a seal simultaneously with the electrical connection of the die to the substrate.
Yet another drawback of the prior art package is the widespread use of solder alloys containing lead, primarily because of the relatively low melting temperature of lead and the relatively high strength of the joints formed thereof when solidified. Lead is toxic and can have a significant, long-term adverse impact on the environment when electronic devices with solder joints containing lead are disposed of, e.g., in landfills. It is therefore desirable to provide a method of soldering a semiconductor die to a substrate using electrically conductive alloys that have relatively low melting temperatures, relatively high joint strength when solidified, but which contain no lead or other element that is harmful to the environment when disposed of.